1. Field of the Invention
The present invention generally relates to data processing systems and more particularly to delay line clock systems utilizing and controlling the transfer of information from such data processing systems.
While the invention has particular application for generating timing signals for data processing systems and will be described hereinafter for such use, it is to be understood that the present invention may be utilized to generate timing signals for timing the operation of other devices.
2. Description of the Prior Art
In data processing systems, the transfer of information is particularly controlled by clock pulses derived from clock cycles generated by a clock system. In a typical clock system, the clock generates a rectangular wave train signal, with the signal being in a high state for a portion of the clock cycle and the signal being in a low state for the remainder of the clock cycle. In this type of clock system, the change of the clock signal from the high to the low state or from the low to high state is used to trigger various circuits within the data processing system, including the latching of registers and the clocking of flip-flops. In addition, the high or low state of the clock signal may be used to enable various gates within the data processing system. The period of the clock cycle of a data processing system is usually chosen to match the speed of the logic circuits used in a central processing unit (CPU). Since data processing system timing and control are directly dependent on the clock system signal, the clock signal must be highly reliable and stable.
In microprogrammed data processing systems, the execution time of the various microoperations will usually vary in accordance with the complexity of the microoperation performed. The more complex operations usually require more time to allow the signals to propagate through the increased number of logic gates involved. To maximize performance of a microprogrammed data processing system, it is desirable to have a clock cycle period available that matches the time required by each distinct microoperation. Although this matching could be accomplished by having multiple clock systems, it is much more desirable, because of circuit component expense and synchronization problems, to have one system from which a variety of predetermined clock cycle periods can be dynamically selected. The selection process should be such that after the microinstruction is read from the microprogram control store, and the particular microoperations to be performed by the microinstruction are determined, the clock cycle period can be adjusted to permit sufficient time, but not excessive time, to complete the particular microoperations in the process of being executed. The clock cycle period can be implicitly selected by being associated with the microoperations of the microinstruction with the microoperation decoder providing one or more bits used to select the clock cycle period. In a data processing system that does not overlap the execution of microinstructions, e.g., the next microinstruction being read during the execution of the current microinstruction, it is important that the clock cycle period selection and generation be done within the selected clock cycle period. The speed matching is done so that the clock cycle is sufficiently long to allow data signals the opportunity to propagate through the longest logic path.
In any clock system, particularly when used in a data processing system, the stability of the clock cycle period is important. That is, it is desirable that the clock cycle period vary as little as possible due to variation in component operating temperature, operating voltage, or the particular component used in fabrication of a particular clock system. Each component used in fabricating a clock system has its own propagation time tolerances. Because the summation of the individual propagation time tolerances of each component used in a path of a clock system circuit is used to determine the worst case timing of a clock system, it follows that reducing the number of components in each path will lead to increased clock stability. Stability can also be increased by choosing components which inherently have narrower tolerances than other components. For example, it may be desirable in a clock system circuit to use a delay line which has a typical propagation time tolerance of plus or minus 5% due to voltage and temperature variations rather than multivibrators or one shots which have looser typical propagation time tolerances.
A clock system in a data processing system is generally inhibited from generating clock pulses when information is not to be strobed into a receiving element, so as to prevent the transfer of erroneous information or loss of information thereby creating an error condition. Accordingly, a stall signal or condition is generated. A typical example of a stall condition may be, for example, that condition under which a utilizing element such as a CPU is waiting for the data processing system's memory to provide information thereto. When the receiving element is expecting the information from the memory, a clock pulse is not generated for strobing the information to the receiving element, particularly if there is an indication that the memory will not be providing such information for possibly another clock cycle. Accordingly, a stall condition is generated that will stall the clock by preventing the clock's rectangular wave train signal from changing state, thereby stalling the generation of further clock pulses. By providing a stall high signal that stalls the clock's rectangular wave train signal in the high state, the high to low clock pulse can be inhibited. By providing a stall low signal that stalls the clock's rectangular wave train signal in the low state, the low to high clock pulse can be inhibited. These stall conditions however, upon an indication that the information will be presently transferred, will be cleared so as to generate another clock cycle and the pulses derived therefrom. It is important in such clock systems that the clock cycle be able to start up again in a minimum period of time after the removal of the stall condition. An example of a stallable clock system is given in U.S. Pat. No. 4,134,073 entitled "Clock System Having Adaptive Synchronization Feature" issued to William W. MacGregor and incorporated herein by reference.
By minimizing the number of components and by using components with inherently narrower tolerances in the clock system circuit, manufacturing economy can be achieved and a need to individually tune each clock system to the specified clock period can be eliminated. An example of a stallable clock having dynamically selectable clock periods which utilizes a minimum number of narrower tolerance components is given in U.S. Pat. No. 4,241,418 entitled "Clock System Having a Dynamically Selectable Clock Period" issued to Philip E. Stanley and incorporated herein by reference.
As performance of data processing systems is improved by use of faster circuit components in the logic circuits, the clock cycle periods used in the CPU become shorter and accumulative tolerance that must be allowed due to component variations in the clock system circuit becomes a larger percentage of the total clock cycle period. For example, the variation may be plus or minus 5 nanoseconds in a 100 nanosecond clock cycle period for a data processing system designed for a minimum 95 nanosecond clock cycle period results in a plus or minus 5% variation in the clock cycle period. The same plus or minus 5 nanosecond variation in a 50 nanosecond clock cycle period results in a plus or minus 10% variation in the clock cycle period in a system designed for a minimum 45 nanosecond clock cycle period. If the clock can be adjusted during manufacturing to have a 45 nanosecond clock cycle period with a tolerance of -0 nanoseconds and +2 nanoseconds, the throughput of the worst case data processing system with an adjustable clock cycle period, one having a clock cycle period of 47 nanoseconds (45+2), can be up to 17.7% ((55-47)/45*100) better than a data processing system having a non-adjustable clock with the worst case clock cycle period of 55 nanoseconds (50+5).
Therefore, although it is desirable as mentioned hereinbefore not to have to individually adjust the clock cycle period of the system clock during manufacture, adjustment is necessary in order to maximize the throughput of the data processing system. An example of the clock system providing for the adjustment of the clock frequency is given in U.S. Pat. No. 3,775,696 entitled "Synchronous Digital System Having a Multi-Speed Logic Clock Oscillator" issued to Emory Carl Grath and incorporated herein by reference. In the clock system of U.S. Pat. No. 3,775,696, an adjustable delay line is connected in series with a fixed delay line with the output of the delay lines being fed as input to a NAND gate and the output of a NAND gate being fed as input to the delay lines as well as being used for the clock signal. In this device, the adjustable delay line is comprised of a plurality of selected lengths of copper transmission line which are etched onto any epoxy-glass circuit board onto which the remaining components are mounted, with each transmission line connecting a pair of plated terminals which extend through the printed circuit board. The propagation delay of copper etch on epoxy-glass circuit boards is approximately six inches per nanosecond, such that each foot of transmission line introduces a two nanosecond time delay. The transmission line lengths are adaptable to be selectively interconnected by connecting the appropriate terminals, thereby introducing accumulative time delays. The lengths of the transmission line segment are binary weighted to allow introduction of a desired time delay with a minimum number of interconnections. The plurality of plated holes at the ends of the lengths of copper transmission line which comprise the adjustable delay line may be interconnected by short wire jumpers while only introducing negligible time delays.
Although the clock system of U.S. Pat. No. 3,775,696 is adjustable, it has several disadvantages. To provide for an adjustment of plus or minus 12 nanoseconds, a span of 24 nanoseconds, a minimum of 12 feet of copper etch transmission line is required and providing this may present significant problems in laying out the circuit board as more and more complex, circuits requiring more interconnects are used. In addition, the adjustment of the clock during manufacture by the placing of jumpers can be time consuming and therefore costly. Further the clock system can not be easily adjusted in the field during system maintenance to compensate for changes in clock speed due to components aging or replacement. Also the clock system can not be easily adjusted to operate the data processing system at marginal speeds to detect speed dependent problems before they impair the data processing system performance at normal operating speed.